Skip to search form Skip to main content. Sapatnekar A dissertation submitted to the faculty of the graduate school of the university of minnesota Under the sustained progress in VLSI technology, interconnect wires become increasingly important to system performance.
This thesis presents research work on several aspects of VLSI interconnect performance optimization, namely, single-net performance driven routing, routing in the presence of buffer blockages and bays, performance driven multi-net global routing and interconnect planning. From This Paper Figures, tables, and topics from this paper. Routing Search source additional papers on this topic.
Topics Discussed in This Paper.
Very-large-scale integration Maximum flow problem Network congestion Tree data structure Numerous Wiring. References Publications referenced by this paper. Showing of 72 references.
Near-optimal critical sink routing tree constructions Kenneth D. BoeseAndrew B.
KahngBernard A. Network flows - theory, algorithms and applications Ravindra K. AhujaThomas L. MagnantiJames B.
Buffer placement in distributed RC-tree networks for minimal elmore delay. Planning buffer locations by network flows Xiaoping TangMartin D. DraganAndrew B.
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